Vertical FETs with different gate lengths and spacer thicknesses
US10141448B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2017 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Dec 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques for forming VFETs with differing Lg using fins of the same height are provided. In one aspect, a method of forming a VFET device includes: patterning (first/second) fins having a uniform fin height in a substrate; forming bottom source/drains at a base of the fins; forming first bottom spacers on the bottom source/drains; selectively forming second bottom spacers (as a dopant source) at the base of the second fins; driving dopants from the bottom source/drains into the first fins and also from second bottom spacers into the second fins to form bottom junctions having a height H1 and H2, respectively, wherein H2>H1; forming gates along the fins, wherein the gates along the first/second fins have Lg1/Lg2, wherein Lg1>Lg2 based on H2>H1; forming top spacers above the gates; and forming top source and drains above the top spacers. VFET devices are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.