Via and skip via structures
US10157833B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | May 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.