Memory cells and memory arrays
US10157926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2017 |
| Grant date | Dec 18, 2018 |
| Priority date | — |
| Expiry date | Jul 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.