Method of examining locations in a wafer with adjustable navigation accuracy and system thereof
US10161882B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2016 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method, computerized system and computer program product for examining an object using a processor operatively connected to a memory, the method comprising: accommodating in the memory data indicative of a plurality of alignment targets, each alignment target associated with a target location on an object; accommodating in the memory a plurality of locations to be captured; and selecting by the processor an alignment target subset of the plurality of alignment targets, such that each of the plurality of locations is associated with and is within a determined distance from a single alignment target from the alignment target subset, the distance determined in accordance with a provided field of view, and wherein the alignment target subset comprises fewer targets than locations to be reviewed, the alignment target being usable for aligning the object relative to an examination tool for capturing the locations associated with the single alignment target.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.