Hardware apparatuses and methods for memory corruption detection
US10162694B2 · kind B2 · utility
11Cited by
14References
24Claims
0Family size
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Key dates
| Filing date | Dec 21, 2015 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Mar 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.