Periphery fill and localized capacitance
US10163480B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jul 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.