Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US10163826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.