Nanosheet field effect transistors with partial inside spacers
US10170584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jan 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.