Vertical memory cell with non-self-aligned floating drain-source implant
US10192999B2 · kind B2 · utility
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11References
18Claims
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Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.