Method of manufacturing a semiconductor device having a charge compensation region underneath a gate trench
US10199456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Aug 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device is provided. The device includes a semiconductor substrate having a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.