Semiconductor device package having an underfill barrier
US10217649B2 · kind B2 · utility
6Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2017 |
| Grant date | Feb 26, 2019 |
| Priority date | — |
| Expiry date | Jun 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01006
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.