Optimizing data approximation analysis using low bower circuitry
US10224089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2018 |
| Grant date | Mar 5, 2019 |
| Priority date | — |
| Expiry date | Jun 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.