Integration of thick and thin nanosheet transistors on a single chip
US10229971B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes constructing the first nanosheet transistor by forming a first nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate and first spacers over the first nanosheet stack, selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material, filling the gaps with second spacers, removing the dummy gate, removing a portion of the first nanosheet stack including layers of the first and second materials, and selectively removing remaining layers of the second material such that a single layer of the first material remains intact to define a single nanosheet channel. The method includes constructing the second nanosheet transistor by forming a second nanosheet stack having multiple layers of nanosheet channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.