Operation of a multi-slice processor with reduced flush and restore latency

US10241790B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Salma Ayub · Austin, US
• Brian D. Barrick · Pflugerville, US
• Joshua W. Bowman · Austin, US
• Sundeep Chadha · Austin, US
• Cliff Kucharski · Austin, US
• Dung Q. Nguyen · Austin, US
• David R. Terry · Austin, US
• Jing Zhang · Poughkeepsie, US

Key dates

• Filing date: Dec 15, 2015
• Grant date: Mar 26, 2019
• Expiry date: Sep 3, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3891
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.