Operation of a multi-slice processor with reduced flush and restore latency
US10248421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Jul 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes execution slices and load/store slices coupled via a results bus, including: for a target instruction targeting a logical register, determining whether an entry in a general purpose register representing the logical register is pending a flush; if the entry in the general purpose register representing the logical register is pending a flush: cancelling the flush in the entry of the general purpose register; storing the target instruction in the entry of the general purpose register representing the logical register, and if an entry in a history buffer targeting the logical register is pending a restore, cancelling the restore for the entry of the history buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.