High performance interconnect

US10248591B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Robert J. Safranek · Portland, US
• Robert G. Blankenship · Tacoma, US
• Venkatraman Iyer · Austin, US
• Jeff Willey · Timnath, US
• Robert Beers · Hillsboro, US
• Darren S. Jue · Sunnyvale, US
• Arvind Kumar · Beaverton, US
• Debendra Das Sharma · Santa Clara, US
• Jeffrey C. Swanson · Sunnyvale, US
• Bahaa Fahim · San Jose, US
• Vedaraman Geetha · Fremont, US
• Aaron T. Spink · San Francisco, US
• Fulvio Spagna · San Jose, US
• Rahul R. Shah · Marlborough, US
• Sitaraman V. Iyer · San Jose, US
• William Harry Nale · Livermore, US
• Abhishek Das · Damoh, IN
• Simon P. Johnson · Beaverton, US
• Yuvraj S. Dhillon · Hillsboro, US
• Yen-Cheng Liu · Portland, US
• Raj K. Ramanujan · Federal Way, US
• Robert A. Maddox · Columbia, US
• Herbert Hum · Portland, US
• Ashish Gupta · San Jose, US

Key dates

• Filing date: Dec 28, 2016
• Grant date: Apr 2, 2019
• Expiry date: Mar 19, 2037

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D30/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.