Tungsten feature fill with nucleation inhibition

US10256142B2 · kind B2 · utility

Assignee

• Novellus Systems, Inc. · US

Inventors

• Anand Chandrashekar · Sunnyvale, US
• Esther Jeng · Los Altos, US
• Raashina Humayun · Los Altos, US
• Michal Danek · Cupertino, US
• Juwen Gao · San Jose, US
• Deqi Wang · San Jose, US

Key dates

• Filing date: Feb 22, 2013
• Grant date: Apr 9, 2019
• Expiry date: Aug 20, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.