Energy efficient processor core architecture for image processor
US10275253B2 · kind B2 · utility
1Cited by
32References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | Aug 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N3/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus that includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.