Daniel Frederic Finchelstein
39Patents
7h-index
23Co-inventors
65Inventor score
Filing activity: Mar 11, 2003 → Sep 22, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7508936B2 | Hardware accelerator for elliptic curve cryptography | Physics | 51 | Expired |
| US9772852B2 | Energy efficient processor core architecture for image processor | Electricity | 10 | Active |
| US10546211B2 | Convolutional neural network on programmable two dimensional image processor | Physics | 10 | Active |
| US9749548B2 | Virtual linebuffers for image signal processors | Physics | 8 | Active |
| US9756268B2 | Line buffer unit for image processor | Electricity | 8 | Active |
| US10915773B2 | Statistics operations on two dimensional image processor | Physics | 8 | Active |
| US9769356B2 | Two dimensional shift array for image processor | Physics | 7 | Active |
| US10321077B2 | Line buffer unit for image processor | Electricity | 6 | Active |
| US10277833B2 | Virtual linebuffers for image signal processors | Physics | 6 | Active |
| US9986187B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 4 | Active |
| US10334194B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 4 | Active |
| US9965824B2 | Architecture for high performance, power efficient, programmable image processing | Emerging Cross-Sectional Technologies | 3 | Active |
| US10387989B2 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Physics | 2 | Active |
| US10516833B2 | Virtual linebuffers for image signal processors | Physics | 2 | Active |
| US10291813B2 | Sheet generator for image processor | Physics | 2 | Active |
| US9978116B2 | Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 2 | Active |
| US10489878B2 | Configurable and programmable image processor unit | Electricity | 1 | Active |
| US10275253B2 | Energy efficient processor core architecture for image processor | Electricity | 1 | Active |
| US10531030B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 1 | Active |
| US10387988B2 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Physics | 0 | Active |
| US9383968B2 | Math processing by detection of elementary valued operands | Physics | 0 | Active |
| US11153464B2 | Two dimensional shift array for image processor | Physics | 0 | Active |
| US10095479B2 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Physics | 0 | Active |
| US10791284B2 | Virtual linebuffers for image signal processors | Physics | 0 | Active |
| US10417732B2 | Architecture for high performance, power efficient, programmable image processing | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.