Method of making split gate non-volatile flash memory cell
US10276696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2017 |
| Grant date | Apr 30, 2019 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.