Inventor · Shanghai, CN

Leo Xing

20Patents
2h-index
13Co-inventors
46Inventor score

Filing activity: Apr 22, 2017 → Jun 7, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US11316024B2 Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same Physics 3 Active
US10879252B2 Non-volatile memory cells with floating gates in dedicated trenches Electricity 2 Active
US11315635B2 Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same Physics 2 Active
US11737266B2 Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate Electricity 1 Active
US10644139B2 Method of making split gate non-volatile flash memory cell Electricity 1 Active
US11322507B2 Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks Electricity 1 Active
US10615270B2 Method of making split gate non-volatile flash memory cell Electricity 1 Active
US11081553B2 Method of forming split gate memory cells Electricity 1 Active
US10600794B2 Twin bit non-volatile memory cells with floating gates in substrate trenches Electricity 0 Active
US10833178B2 Method of making split gate non-volatile flash memory cell Electricity 0 Active
US11404545B2 Method of forming split-gate flash memory cell with spacer defined floating gate and discretely formed polysilicon gates Electricity 0 Active
US12144172B2 Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate using a dummy area Electricity 0 Active
US10276696B2 Method of making split gate non-volatile flash memory cell Electricity 0 Active
US11621335B2 Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates Physics 0 Active
US11508442B2 Non-volatile memory system using strap cells in source line pull down circuits Physics 0 Active
US11799005B2 Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same Electricity 0 Active
US11444091B2 Method of making memory cells, high voltage devices and logic devices on a substrate Electricity 0 Active
US11315940B2 Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and FinFET logic devices Electricity 0 Active
US10833179B2 Method of making split gate non-volatile flash memory cell Electricity 0 Active
US11968829B2 Method of forming memory cells, high voltage devices and logic devices on a semiconductor substrate Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.