Low voltage, master-slave flip-flop

US10277207B1 · kind B1 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Alok Tripathi · Beaverton, US
• Amit Verma · Schweinhub, DE
• Anuj Grover · New Delhi, IN
• Deepak Kumar Bihani · Noida, IN
• Tanmoy Roy · Mountain View, US
• Tanuj Agrawal · Noida, IN

Key dates

• Filing date: Feb 8, 2018
• Grant date: Apr 30, 2019
• Expiry date: Feb 8, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/412
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.