Page faulting and selective preemption
US10282812B2 · kind B2 · utility
2Cited by
0References
20Claims
0Family size
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Key dates
| Filing date | Apr 9, 2017 |
| Grant date | May 7, 2019 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4843
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.