Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks
US10290364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2015 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Sep 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.