Method for etching high-K dielectric using pulsed bias power
US10290506B2 · kind B2 · utility
35Cited by
4References
23Claims
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Key dates
| Filing date | Feb 13, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.