Alok Ranjan
120Patents
14h-index
73Co-inventors
85Inventor score
Filing activity: Aug 25, 2011 → May 23, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10998169B2 | Systems and methods of control for plasma processing | Electricity | 40 | Active |
| US9666447B2 | Method for selectivity enhancement during dry plasma etching | Electricity | 37 | Active |
| US8735291B2 | Method for etching high-k dielectric using pulsed bias power | Electricity | 37 | Active |
| US9570313B2 | Method for etching high-K dielectric using pulsed bias power | Electricity | 37 | Active |
| US9607843B2 | Method for roughness improvement and selectivity enhancement during arc layer etch via adjustment of carbon-fluorine content | Electricity | 36 | Active |
| US10063062B2 | Method of detecting plasma discharge in a plasma processing system | Electricity | 35 | Active |
| US10290506B2 | Method for etching high-K dielectric using pulsed bias power | Electricity | 35 | Active |
| US9159575B2 | Method for etching high-K dielectric using pulsed bias power | Electricity | 35 | Active |
| US9530667B2 | Method for roughness improvement and selectivity enhancement during arc layer etch using carbon | Electricity | 35 | Active |
| US9576816B2 | Method for roughness improvement and selectivity enhancement during arc layer etch using hydrogen | Electricity | 35 | Active |
| US9111746B2 | Method for reducing damage to low-k gate spacer during etching | Electricity | 27 | Active |
| US9768033B2 | Methods for high precision etching of substrates | Electricity | 27 | Active |
| US9318343B2 | Method to improve etch selectivity during silicon nitride spacer etch | Electricity | 25 | Active |
| US8906760B2 | Aspect ratio dependent deposition to improve gate spacer profile, fin-loss and hardmask-loss for FinFET scheme | Electricity | 17 | Active |
| US8551877B2 | Sidewall and chamfer protection during hard mask removal for interconnect patterning | Electricity | 9 | Active |
| US8592327B2 | Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage | Electricity | 8 | Active |
| US10701103B2 | Securing devices using network traffic analysis and software-defined networking (SDN) | Electricity | 6 | Active |
| US9054050B2 | Method for deep silicon etching using gas pulsing | Electricity | 6 | Active |
| US9378975B2 | Etching method to form spacers having multiple film layers | Electricity | 6 | Active |
| US8809194B2 | Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch | Emerging Cross-Sectional Technologies | 5 | Active |
| US10237916B2 | Systems and methods for ESC temperature control | Electricity | 4 | Active |
| US10529589B2 | Method of plasma etching of silicon-containing organic film using sulfur-based chemistry | Electricity | 4 | Active |
| US9155183B2 | Adjustable slot antenna for control of uniformity in a surface wave plasma source | Electricity | 3 | Active |
| US9779952B2 | Method for laterally trimming a hardmask | Electricity | 3 | Active |
| US10366902B2 | Methods for cyclic etching of a patterned layer | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.