Scalable silicon based resistive memory device
US10290801B2 · kind B2 · utility
2Cited by
212References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2015 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Feb 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.