Patent · US Active

Multiply-add operations of binary numbers in an arithmetic unit

US10296294B2 · kind B2 · utility

2Cited by

3References

1Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Tina Babinsky · Steinenbronn, DE
Michael Klein · Schenefeld, DE
Cedric Lichtenau · Stuttgart, DE
Silvia M. Mueller · Altdorf, DE

Key dates

Filing date	Feb 15, 2018
Grant date	May 21, 2019
Priority date	—
Expiry date	Feb 15, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/49
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.