CMOS image sensor with buried superlattice layer to reduce crosstalk

US10304881B1 · kind B1 · utility

Assignee

• ATOMERA INCORPORATED · US

Inventors

• Yi-Ann Chen · Campbell, US
• Abid Husain · San Jose, US
• Hideki Takeuchi · Sakaki, JP

Key dates

• Filing date: Dec 15, 2017
• Grant date: May 28, 2019
• Expiry date: Dec 15, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/8063

Abstract

A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a superlattice on the semiconductor substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The image sensor may further include a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.