Three-dimensional pattern risk scoring
US10311186B2 · kind B2 · utility
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Key dates
| Filing date | Apr 12, 2016 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jun 10, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.