Memory including side-car arrays with irregular sized entries
US10311191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2017 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jun 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.