Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling
US10312246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2015 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Nov 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.