Ensuring forward progress for nested translations in a memory management unit
US10318435B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Sep 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Ensuring forward progress for nested translations in a memory management unit (MMU) including receiving a plurality of nested translation requests, wherein each of the plurality of nested translation requests requires at least one congruence class lock; detecting, using a congruence class scoreboard, a collision of the plurality of nested translation requests based on the required congruence class locks; quiescing, in response to detecting the collision of the plurality of nested translation requests, a translation pipeline in the MMU including switching operation of the translation pipeline from a multi-thread mode to a single-thread mode and marking a first subset of the plurality of nested translation requests as high-priority nested translation requests; and servicing the high-priority nested translation requests through the translation pipeline in the single-thread mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.