Semiconductor wafer and method for processing a semiconductor wafer

US10325803B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Matthias Kuenle · Villach, AT
• Gerhard Schmidt · Graz, AT
• Martin Sporn · Villach, AT
• Markus Kahn · Rangersdorf, AT
• Juergen Steinbrenner · Zistersdorf, AT
• Ravi Keshav Joshi · Klagenfurt, AT

Key dates

• Filing date: May 3, 2018
• Grant date: Jun 18, 2019
• Expiry date: May 3, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/024
• WIPO field: Surface technology, coating
• WIPO sector: Chemistry

Abstract

According to various embodiments, a semiconductor wafer may include: a semiconductor body including an integrated circuit structure; and at least one tetrahedral amorphous carbon layer formed at least one of over or in the integrated circuit structure, the at least one tetrahedral amorphous carbon layer may include a substance amount fraction of sp3-hybridized carbon of larger than approximately 0.4 and a substance amount fraction of hydrogen smaller than approximately 0.1.