Field-effect transistors with fins having independently-dimensioned sections
US10325811B2 · kind B2 · utility
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19References
17Claims
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Key dates
| Filing date | Oct 26, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Oct 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.