Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register
US10334194B2 · kind B2 · utility
4Cited by
33References
6Claims
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Key dates
| Filing date | Apr 5, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Apr 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.