William R. Mark
27Patents
6h-index
35Co-inventors
69Inventor score
Filing activity: Sep 19, 1997 → Sep 22, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5915987A | Latched electrical connector | Electricity | 71 | Expired |
| US7567248B1 | System and method for computing intersections between rays and surfaces | Physics | 31 | Expired |
| US7463259B1 | Subshader mechanism for programming language | Physics | 23 | Expired |
| US7268785B1 | System and method for interfacing graphics program modules | Physics | 14 | Expired |
| US6781391B2 | Multi-channel, low input capacitance signal probe and probe head | Physics | 10 | Expired |
| US10546211B2 | Convolutional neural network on programmable two dimensional image processor | Physics | 10 | Active |
| US10334194B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 4 | Active |
| US9986187B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 4 | Active |
| US9965824B2 | Architecture for high performance, power efficient, programmable image processing | Emerging Cross-Sectional Technologies | 3 | Active |
| US6847199B2 | Capturing both digital and analog forms of a signal through the same probing path | Physics | 3 | Expired |
| US10387989B2 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Physics | 2 | Active |
| US9978116B2 | Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 2 | Active |
| US10531030B2 | Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register | Physics | 1 | Active |
| US10733956B2 | Macro I/O unit for image processor | Electricity | 1 | Active |
| US10489878B2 | Configurable and programmable image processor unit | Electricity | 1 | Active |
| US10719905B2 | Architecture for high performance, power efficient, programmable image processing | Emerging Cross-Sectional Technologies | 0 | Active |
| US10380969B2 | Macro I/O unit for image processor | Electricity | 0 | Active |
| US11250537B2 | Configurable and programmable image processor unit | Electricity | 0 | Active |
| US10387988B2 | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform | Physics | 0 | Active |
| US12020027B2 | Convolutional neural network on programmable two dimensional image processor | Physics | 0 | Active |
| US10685423B2 | Determination of per line buffer unit memory allocation | Emerging Cross-Sectional Technologies | 0 | Active |
| US10430919B2 | Determination of per line buffer unit memory allocation | Emerging Cross-Sectional Technologies | 0 | Active |
| US10789505B2 | Convolutional neural network on programmable two dimensional image processor | Physics | 0 | Active |
| US10417732B2 | Architecture for high performance, power efficient, programmable image processing | Emerging Cross-Sectional Technologies | 0 | Active |
| US10504480B2 | Macro I/O unit for image processor | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.