Patent · US Active

Methods, apparatus and system for self-aligned metal hard masks

US10340142B1 · kind B1 · utility

2Cited by
2References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 12, 2018
Grant dateJul 2, 2019
Priority date
Expiry dateMar 12, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/017
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

At least one method, apparatus and system disclosed herein involves forming semiconductor devices comprising vertically aligned gates, metal hard masks, and nitride regions. The semiconductor device may contain a semiconductor substrate; a gate disposed on the semiconductor substrate; a metal hard mask vertically aligned with the gate; a nitride region vertically aligned with the gate and the metal hard mask; and source/drain (S/D) regions disposed in proximity to the gate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.