Method to co-integrate SiGe and Si channels for finFET devices
US10340195B2 · kind B2 · utility
3Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 14, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Nov 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.