Inventor · Schenectady, NY, US

Prasanna Khare

49Patents
8h-index
15Co-inventors
68Inventor score

Filing activity: May 22, 2008 → Feb 21, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8956942B2 Method of forming a fully substrate-isolated FinFET transistor Electricity 35 Active
US8759874B1 FinFET device with isolated channel Electricity 30 Active
US9093496B2 Process for faciltiating fin isolation schemes Electricity 17 Active
US8828851B2 Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering Electricity 12 Active
US9166023B2 Bulk finFET semiconductor-on-nothing integration Electricity 11 Active
US9012999B2 Semiconductor device with an inclined source/drain and associated methods Electricity 10 Active
US9349730B2 Fin transformation process and isolation structures facilitating different Fin isolation schemes Electricity 9 Active
US9093556B2 Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods Electricity 9 Active
US9520393B2 Fully substrate-isolated FinFET transistor Electricity 7 Active
US9685380B2 Method to co-integrate SiGe and Si channels for finFET devices Electricity 6 Active
US9171757B2 Dual shallow trench isolation liner for preventing electrical shorts Electricity 6 Active
US8703550B2 Dual shallow trench isolation liner for preventing electrical shorts Electricity 6 Active
US8187975B1 Hydrochloric acid etch and low temperature epitaxy in a single chamber for raised source-drain fabrication Electricity 6 Active
US9000555B2 Electronic device including shallow trench isolation (STI) regions with bottom nitride liner and upper oxide liner and related methods Electricity 5 Active
US9082788B2 Method of making a semiconductor device including an all around gate Electricity 5 Active
US9437504B2 Method for the formation of fin structures for FinFET devices Electricity 4 Active
US9620507B2 Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region Electricity 4 Active
US10062690B2 Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods Electricity 4 Active
US10340195B2 Method to co-integrate SiGe and Si channels for finFET devices Electricity 3 Active
US10170546B2 Fully substrate-isolated FinFET transistor Electricity 3 Active
US9099570B2 Method for the formation of dielectric isolated fin structures for use, for example, in FinFET devices Electricity 3 Active
US10170475B2 Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region Electricity 2 Active
US9502292B2 Dual shallow trench isolation liner for preventing electrical shorts Electricity 2 Active
US9252052B2 Dual shallow trench isolation liner for preventing electrical shorts Electricity 2 Active
US9000491B2 Layer formation with reduced channel loss Electricity 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.