Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC
US10354733B1 · kind B1 · utility
17Cited by
6References
20Claims
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Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Jul 16, 2019 |
| Priority date | — |
| Expiry date | Oct 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described for partitioning and reordering block-based matrix multiplications for high-speed data streaming in general matrix multiplication (GEMM), which may be implemented by a programmable integrated circuit (IC). By preloading and hierarchically caching the blocks, examples of the present disclosure reduce the double data rate (DDR) memory intake bandwidth for software-defined GEMM accelerators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.