Error handling in transactional buffered memory
US10360096B2 · kind B2 · utility
0Cited by
9References
23Claims
0Family size
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Key dates
| Filing date | Mar 17, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jul 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0097
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.