Vertical transport FET with two or more gate lengths
US10361127B1 · kind B1 · utility
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12References
13Claims
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Key dates
| Filing date | Dec 28, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Dec 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/013
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a device with multiple gate lengths includes forming a gate stack on vertical fins. A cutting mask formed on the gate stack is etched to include two or more different heights. Gate structures with two or more gate lengths are etched by employing the two or more different heights in the cutting mask as an etch mask. The cutting mask is removed. A top source/drain regions is formed on top of the vertical fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.