Timing closure of circuit designs for integrated circuits
US10366201B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2017 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Apr 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Closing timing for a circuit design can include displaying, using a display device, a first region having a plurality of controls corresponding to a plurality of data sets generated at different times during a phase of a design flow for a circuit design, wherein each control selects a data set associated with the control, and displaying, using the display device, a second region configured to display a list of critical paths for data sets selected from the first region using one of the plurality of controls. Closing timing further can include displaying, using the display device, a third region configured to display a representation of a target integrated circuit including layouts for the critical paths of the list for implementations of the circuit design specified by the selected data sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.