CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice

US10367028B2 · kind B2 · utility

Assignee

• ATOMERA INCORPORATED · US

Inventors

• Yi-Ann Chen · Campbell, US
• Abid Husain · San Jose, US
• Hideki Takeuchi · Sakaki, JP

Key dates

• Filing date: Dec 15, 2017
• Grant date: Jul 30, 2019
• Expiry date: Dec 15, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/014

Abstract

A CMOS image sensor may include a first semiconductor chip including image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions and a superlattice channel extending between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Each transistor may further include a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.