Method of forming vias in silicon carbide and resulting devices and circuits
US10367074B2 · kind B2 · utility
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57References
9Claims
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Key dates
| Filing date | Sep 26, 2016 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Sep 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.