Patent · US Active

Integrated circuit package configurations to reduce stiffness

US10373844B2 · kind B2 · utility

0Cited by

2References

4Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Sven Albers · Regensburg, DE
Sonja Koller · Regensburg, DE
Thorsten Meyer · Regensburg, DE
Georg Seidemann · Landshut, DE
Christian Geissler · Teugn, DE
Andreas Wolter · Regensburg, DE

Key dates

Filing date	May 9, 2017
Grant date	Aug 6, 2019
Priority date	—
Expiry date	May 9, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.