Transistor fin formation via cladding on sacrificial core

US10373977B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Daniel B. Aubertine · North Plains, US
• Tahir Ghani · Portland, US
• Jack T. Kavalieros · Portland, US
• Benjamin Chu-Kung · Portland, US
• Chandra S. Mohapatra · Hillsboro, US
• Karthik Jambunathan · Hillsboro, US
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US

Key dates

• Filing date: Jun 26, 2015
• Grant date: Aug 6, 2019
• Expiry date: Jun 26, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/121
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.