Methods of shielding an embedded MRAM array on an integrated circuit product comprising CMOS based transistors
US10374154B1 · kind B1 · utility
1Cited by
17References
16Claims
0Family size
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Key dates
| Filing date | Jan 18, 2018 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Jan 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.