Dual port static random access memory (DPSRAM) cell
US10381056B2 · kind B2 · utility
4Cited by
1References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.